Software cache coherency schemes are implemented in software and uses a cache flush or cache invalidate instruction supported by hardware. If one processor reads/writes an address and caches the copy in its local cache, the software will need to execute a “cache flush” or “cache invalidate” for that address and make sure the latest data is written to memory before another processor can use that same address.

Now that means more instructions to execute (making this slower) and more complexity if more address space is shared across caches to keep track of all of these addresses. Hence software based schemes are not commonly used in a single chip/cluster that has several processors/caches.